In packaging microelectronic devices, such as packaging integrated circuit chips en printed circuit boards, the integrated circuit chips are generally mounted parallel to and facing the printed circuit board such that faces of the integrated circuit chips are adjacent a face of the circuit board. This packaging technology allows a large number of input/output connections between the integrated circuit chips and the printed circuit board, especially when solder bump technology is used over the entire face of the integrated circuit chips. However, this technology may limit a packaging density, because the large faces of the integrated circuit chips are mounted adjacent the face of the printed circuit board.
To increase the packaging density of chips on a printed circuit board, three-dimensional packaging has been proposed, wherein the chips are mounted orthogonal to the circuit board so that edges of the chips are adjacent the face of the circuit board. See, for example, U.S. Pat. No. 5,347,428 to Carson et al. entitled “Module Comprising IC Memory Stack Dedicated to and Structurally Combined With an IC Microprocessor Chip” and U.S. Pat. No. 5,432,729 to Carson et al. entitled “Electronic Module Comprising a Stack of IC Chips Each Interacting With an IC Chip Secured to the Stack”, both of which are assigned to Irvine Sensors Corporation. In these patents, solder bumps are used to connect the edges, rather than the faces of integrated circuit chips to a substrate. Unfortunately, an edge-to-face connection may be difficult and costly to produce.
U.S. Pat. No. 5,113,314 to Wheeler et al. entitled “High Speed, High Density Chip Mounting” describes another three-dimensional packaging technique. The '314 patent describes a plurality of integrated circuit chips whose active faces are perpendicular to a chip carrier. Solder bumps are used to connect pads on the chips to pads on the substrate.
An issue in using solder bump technology to interconnect a three-dimensional package is how to get the solder bump to bridge from one substrate to another. In particular, it may be difficult to form solder which extends beyond the edge of a chip because a chip sawing or dicing operation may remove solder which extends beyond the chip edge. Moreover, during solder reflow, the solder may take the shape of a hemisphere or partial hemisphere on a contact pad. Thus, it may be difficult to cause the solder on one contact pad to extend onto another contact pad, in a three-dimensional package. Even if solder is placed on a pair of adjacent contact pads in a three-dimensional package, it may be difficult to cause the reflowed solder to join up, rather than forming individual solder bumps.
Solder interconnections are also discussed in U.S. Pat. Nos. 5,793,116; 6,418,033; and 6,392,163. Each of these patents are assigned to the assignee of the present invention, and the disclosures of each of these patents are hereby incorporated herein in their entirety by reference.